Module polynomial 

Redundant polynomial representation for hardware arithmetic.

The hardware represents 256-bit field elements as polynomials with NUM_COEFFS coefficients of COEFF_BITS bits each. This redundant representation avoids long carry chains in the critical path, enabling higher clock frequencies.

Parameters (matching the SystemVerilog mrt_pkg)

• TargetBits = 256
• WordBits = 16
• RedundantBits = 1
• ExtraCoeffs = 1
• NumCoeffs = ceil(256 / 16) + 1 = 17
• CoeffBits = 16 + 1 = 17

Structs

PolyElement

A field element in redundant polynomial form.

Constants

COEFF_BITS

Total bits per coefficient.

COEFF_MASK 🔒

Mask for a single coefficient value.

EXTRA_COEFFS

Extra coefficients beyond ceil(target_bits / word_bits).

NUM_COEFFS

Total number of coefficients per polynomial.

REDUNDANT_BITS

Number of redundant bits per coefficient (carry absorption).

WORD_BITS

Number of data bits per coefficient word.